The present invention generally relates to a clock (or clock signal) supply apparatus destined for use in a system having a sleep operation mode and a non-sleep operation mode, and more particularly to a clock supply apparatus of which power consumption can be reduced during a sleep period (i.e., in the sleep operation mode).
For affording a better understanding of the present invention, a conventional clock supply apparatus known heretofore will briefly be reviewed. FIG. 2 is a block diagram showing, by way of example, a configuration of a system equipped with a conventional clock supply apparatus, the principle of which will be described below on the presumption that the circuits constituting the clock supply apparatus shown in FIG. 2 are implemented in the form of CMOS (complementary metal oxide semiconductor) digital circuits. Accordingly, when the clock supply to the circuits is interrupted, the power consumption must be zero in principle. On the other hand, the power consumption increases as the driving clock rate (frequency of the clock signal) becomes higher.
The system shown in FIG. 2 comprises a clock supply apparatus 211 and a signal processing block 206, wherein the clock supply apparatus 211 supplies a high-rate (high-frequency) clock signal 208 to be utilized for signal processing performed by the signal processing block 206 in the non-sleep mode, while the supply of the high-rate clock signal 208 to the signal processing block 206 is stopped in the sleep mode.
The clock supply apparatus includes a high-rate source clock generating unit 201 for generating a high-rate (high-frequency) source clock signal 207 and a frequency multiplication/division unit 202 in which the high-rate source clock signal 207 undergoes a frequency multiplication/division processing, which results in generation of a high-rate clock signal 208 suited for the signal processing. The high-rate clock signal 208 has a frequency which satisfies the processing rate required by the signal processing block 206. A clock interrupting unit 203 constituting a part of the clock supply apparatus is designed so as to supply the high-rate clock signal 208 to the signal processing block 206 only during a period in which a sleep signal 209 is nonactive.
The clock supply apparatus further includes a sleep time measuring unit 204 which starts a time measurement with the aid of the high-rate clock signal 208 from the moment when the sleep signal 209 becomes active. A sleep end signal 210 is generated after measurement of a predetermined time period. In other words, the period during which the sleep time measuring unit 204 is performing the time measurement represents the sleep period with the other period representing the non-sleep period.
A sleep control unit 205 constituting another part of a clock supply apparatus is in charge of controlling the sleep mode and the non-sleep mode of the signal processing block 206. More particularly, the sleep signal 209 is made active for validating the sleep mode of the signal processing block 206, whereby the supply of the high-rate clock signal 208 to the signal processing block 206 is stopped. Upon detection of the sleep end signal 210, the sleep control unit 205 decides the end of the sleep period to thereby make the sleep signal 209 nonactive. Thus, the supply of the high-rate clock signal 208 to the signal processing block 206 is reopened, which in turn results in restarting of the processing operation of the signal processing block 206.
As is apparent from the above discussion the signal processing block 206 can be set to the complete sleep mode due to the interruption of the supply of the clock in the sleep mode. However, the high-rate source clock generating unit 201, the frequency multiplication/division unit 202 and the sleep time measuring unit 204 of the clock supply apparatus continue to operate at a high clock rate even in the sleep mode in order to measure the sleep time period.
Thus, the conventional clock supply apparatus suffers from a problem in that a relatively high power consumption can not be avoided even during the sleep time period because the high-rate source clock generating unit, the frequency multiplication/division unit and the sleep time measuring unit continue to operate at a high clock rate even in the sleep mode. Consequently, when the clock supply apparatus is employed in an apparatus or system which is designed for continuous operation over an extended time by reducing the power consumption by adopting the sleep mode, as in the case of a portable apparatus or system designed to be driven with a cell, the intrinsic purpose of employing the clock supply apparatus can not be achieved, giving rise to a problem.